forked from I2P_Developers/i2p.i2p
zzz
89e5e1d308
Add output for nativeJcpuidVersion() Change CPUIDCPUInfo back to package private More @since fixes
111 lines
3.6 KiB
C
111 lines
3.6 KiB
C
#include "jcpuid.h"
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/*
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* Versions:
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*
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* 1: Original version
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*
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* 2: (I2P 0.8.7)
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* Add PIC-compatibility
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*
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* 3: (I2P 0.9.25)
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* Added:
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* nativeJcpuidVersion()
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* Set ECX to 0 to support function 7
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*
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*/
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#define JCPUID_VERSION 3
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/* since version 3 */
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JNIEXPORT jint JNICALL Java_freenet_support_CPUInformation_CPUID_nativeJcpuidVersion
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(JNIEnv* env, jclass cls) {
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return (jint) JCPUID_VERSION;
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}
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/**
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From: http://sam.zoy.org/blog/2007-04-13-shlib-with-non-pic-code-have-inline-assembly-and-pic-mix-well
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See also: http://homesource.nekomimicon.net/sourceforum/viewtopic.php?f=15&t=303
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Perhaps the most accessible documentation on what PIC code is and how an ELF dynamic linker works is
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John Levine's Linkers and Loaders (and it has amazing sketches, too!). The Gentoo documentation also
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has an Introduction to Position Independent Code. I'd like to give a few hints on how to fix the
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shlib-with-non-pic-code lintian error caused by inline assembly on the i386 and amd64 platforms,
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as well as build errors that may occur due to inline assembly being used.
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I'm not going to cover the trivial "all objects were not built using gcc's -fPIC flag" problem.
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It usually requires a fix to the build system, not to the code.
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gcc can't find a register (i386)
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PIC on i386 uses a register to store the GOT (global offset table) address.
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This register is usually %ebx, making it unavailable for use by inline assembly
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(and also restricting the compiler's register usage when compiling C or C++ code).
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So the following perfectly valid code will not build with the -fPIC flag:
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void cpuid(uint32_t op, uint32_t reg[4])
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{
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asm volatile("cpuid"
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: "=a"(reg[0]), "=b"(reg[1]), "=c"(reg[2]), "=d"(reg[3])
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: "a"(op)
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: "cc");
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}
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Using -fPIC, gcc will say something around the lines of error: can't find a register in class 'BREG'
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while reloading 'asm'. Several things need to be done to fix this:
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* use a register other than %ebx
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* save %ebx if it risks being clobbered by the assembly code, and don't tell gcc about %ebx at all (it doesn't need to know anyway)
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* if we saved %ebx by pushing it on the stack, make sure the inline assembly code takes the new stack offset into account
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And here is the PIC-compliant version:
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**/
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//Executes the indicated subfunction of the CPUID operation
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JNIEXPORT jobject JNICALL Java_freenet_support_CPUInformation_CPUID_doCPUID
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(JNIEnv * env, jclass cls, jint iFunction)
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{
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int a,b,c,d;
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jclass clsResult = (*env)->FindClass(env, "freenet/support/CPUInformation/CPUID$CPUIDResult");
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jmethodID constructor = (*env)->GetMethodID(env, clsResult,"<init>","(IIII)V" );
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#ifdef _MSC_VER
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//Use MSVC assembler notation
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_asm
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{
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mov eax, iFunction
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// When iFunction is 7, ECX must be 0, just set it all the time
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mov ecx, 0
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cpuid
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mov a, eax
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mov b, ebx
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mov c, ecx
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mov d, edx
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}
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#else
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//Use GCC assembler notation
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asm volatile
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(
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#if (!defined(__X86_64__)) && (!defined(__x86_64__))
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/* 32 bit */
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"pushl %%ebx \n\t" /* save %ebx */
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#endif
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"cpuid \n\t"
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#if (!defined(__X86_64__)) && (!defined(__x86_64__))
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/* 32 bit */
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"movl %%ebx, %1 \n\t" /* save what cpuid just put in %ebx */
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"popl %%ebx \n\t" /* restore the old %ebx */
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: "=a" (a), "=r" (b), "=c" (c), "=d" (d)
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#else
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/* 64 bit */
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: "=a" (a), "=b" (b), "=c" (c), "=d" (d)
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#endif
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/* When iFunction is 7, ECX must be 0, just set it all the time */
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:"a"(iFunction), "c"(0)
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: "cc"
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);
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#endif
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return (*env)->NewObject(env, clsResult,constructor,a,b,c,d);
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}
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